In the past, many specialized logical functions have required dedicated, special-purpose equipments, as for example military controllers, computers, and communications equipment, and those intended for aircraft and spacecraft. The cost of such specialized equipment was previously acceptable in view of the high standards and specialized requirements for such equipment. The specialized requirements might include such considerations as self-testing of each logical function of an assemblage, to thereby verify the entire system. The art of manufacturing integrated circuits for the commercial computer market has advanced so far that, in some cases, the quality and gross performance of commercial logical circuits or functions is equal to, or even superior to, specially-made functions, and due to manufacturing volume, the prices may be much lower for the commercial logic functions. However, the commercial logical functions may not have all of the desired functionalities as those required for specialized high-reliability applications.
U.S. Pat. No. 4,862,072, issued Aug. 29, 1989 in the name of Harris et al. describes a self-test arrangement for an LSI chip containing a number of logical processors. The Harris et al. arrangement uses a plurality of multiplexers connected at various points in the interconnected logical functions to route test signals to certain portions of the circuit, and to couple the resulting response of the portions being tested to an external test bus. As described in the Harris et al. patent, the test bus includes four data paths, and test signals and commands are applied over the four data paths in a manner which allows independent testing of those portions of the processing lying between multiplexers.
Another test bus standard in current use is the IEEE Joint Test Action Group (JTAG) standard. The JTAG standard data rate is so much slower than the speeds at which modern commercial logic functions operate, however, that assemblages including large commercial DRAM, DRAM, ROM, FIFO, multipliers, adders, and the like, may not be testable within reasonable times using JTAG. Nevertheless, for military, aircraft, emergency communication equipment, and the like, the reliability requirements may be such as to require self-test. When the assemblage of equipment communicates among the elements of the assemblage by way of a data bus, it is but a simple matter to connect specialized testers to the bus, to individually test the various elements.
However, in some assemblages, the communication bus may not be externally accessible. This might occur, for example, in a densely packed assemblage containing large numbers of functional elements in the form of solid-state chips. One example of such an assemblage is the high-density interconnect described, for example, in various U.S. patents assigned to Lockheed Martin Corporation or to predecessors thereof, such as U.S. Pat. No. 5,552,633, issued Sep. 3, 1996 in the name of Sharma, in which the interconnections among the various chips are made by multiple layers of printed dielectric film overlying the assemblage.
In an arrangement in which the communication bus by which the various logical functions communicate is not externally accessible, specialized high-speed testers cannot be used to directly test the various logical functions. The speed of the test bus, however, may be insufficient to allow direct testing in a reasonable time of each of the possibly millions of gates of each of tens or hundreds of logical functions. Improved self-test arrangements are desired.